IB Computer Science HL · Year 2 · Lesson 29

CPU architecture, memory and fetch-decode-execute

Computer performance emerges from the interaction of processing, memory, storage and specialized hardware.

Paper 150 minutesA1.1.1 · A1.1.4 · A1.1.5
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Today’s targets

What you need to be able to do

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  • DescribeThe functions and interactions of the main CPU components
  • ExplainThe purposes of different types of primary memory
  • DescribeThe fetch, decode and execute cycle
A1.1.1A1.1.4A1.1.5
Paper 1 lensMatch the depth of every response to the command term. Previously learned content can move quickly, but retrieval must still be accurate.
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Retrieve

Rapid Recall Deck

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Say the answer aloud before flipping. Mark secure knowledge quickly and spend time on the gaps.

  • What are the main roles of the ALU and control unit?: The ALU performs arithmetic and logical operations; the control unit coordinates instruction execution and directs data/control signals.
  • What do the program counter (PC) and instruction register (IR) store?: The PC stores the address of the next instruction; the IR stores the instruction currently being decoded/executed.
  • What do the MAR and MDR store?: The MAR stores the memory address being accessed; the MDR stores data or an instruction being transferred to or from memory.
  • What is the accumulator (AC) used for?: It stores intermediate values or results produced by the ALU.
  • What are the roles of the address, data, and control buses?: The address bus identifies a location; the data bus carries data/instructions; the control bus carries coordination signals such as read/write.
  • How do RAM, ROM, cache, and registers differ?: RAM holds active programs/data; ROM stores persistent instructions/firmware; cache holds frequently needed data near the CPU; registers are the CPU's smallest and fastest working storage.
  • What is a cache hit and a cache miss?: A hit occurs when needed data is found in cache; a miss occurs when it must be fetched from a slower memory level.
  • What are the core stages of the fetch-decode-execute cycle?: Fetch the next instruction from memory, decode what it requires, then execute it; register and bus activity supports each stage.
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A1.1.1 + A1.1.4 · Learn

Core knowledge and application

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A1.1.1Describe

The functions and interactions of the main CPU components

Computer performance emerges from the interaction of processing, memory, storage and specialized hardware.

Exam moveGive a detailed, accurate account of what happens or what something is like.
Required detail 1Units: arithmetic logic unit (ALU), control unit (CU)
Required detail 2Registers: instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC)
Required detail 3Buses: address, data, control
Required detail 4Processors: single core processor, multi-core processor, co-processors
Required detail 5Be able to diagram the relationship between the specified CPU components

Explain it without notes

Describe: The functions and interactions of the main CPU components in the context of a school upgrading computers for graphics, coding and machine learning.

  • Units: arithmetic logic unit (ALU), control unit (CU)
  • Registers: instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC)
  • Buses: address, data, control
  • Processors: single core processor, multi-core processor, co-processors
  • Be able to diagram the relationship between the specified CPU components
A1.1.4Explain

The purposes of different types of primary memory

Computer performance emerges from the interaction of processing, memory, storage and specialized hardware.

Exam moveGive the mechanism or relationship and make the reasons/causes explicit.
Required detail 1Random-access memory (RAM), read only memory (ROM), cache (L1, L2, L3), registers
Required detail 2The interaction of the CPU with different types of memory to optimize performance
Required detail 3The relevance of the terms “cache miss” and “cache hit”

Explain it without notes

Explain: The purposes of different types of primary memory in the context of a school upgrading computers for graphics, coding and machine learning.

  • Random-access memory (RAM), read only memory (ROM), cache (L1, L2, L3), registers
  • The interaction of the CPU with different types of memory to optimize performance
  • The relevance of the terms “cache miss” and “cache hit”
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A1.1.5 · Learn

Core knowledge and application

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A1.1.5Describe

The fetch, decode and execute cycle

Computer performance emerges from the interaction of processing, memory, storage and specialized hardware.

Exam moveGive a detailed, accurate account of what happens or what something is like.
Required detail 1The basic operations a CPU performs to execute a single instruction in machine language
Required detail 2The interaction between memory and registers via the three buses: address, data, control

Explain it without notes

Describe: The fetch, decode and execute cycle in the context of a school upgrading computers for graphics, coding and machine learning.

  • The basic operations a CPU performs to execute a single instruction in machine language
  • The interaction between memory and registers via the three buses: address, data, control
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Worked diagram · A1.1.1 / A1.1.5

CPU components and the fetch–decode–execute path

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Diagrammatic representation of the relationship between the specified CPU components

Main memory
⇄
Address bus
Data bus
Control bus
⇄
CPU
CU · ALU
PC · MAR · MDR · IR · ACC
FetchPC identifies the next instruction; its address is copied to MAR; memory returns the instruction through the data path into MDR and then IR; PC advances.
DecodeThe CU interprets the instruction in IR and prepares the required control signals.
ExecuteThe ALU/other units perform the operation; registers and/or memory are updated.
Trace the busesState when the address bus, data bus and control bus are needed during a memory read.
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2027 Case Study connection

Why generative-image models need serious compute

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Diffusion connectionImage generation can require repeated denoising steps. Each step performs model inference over high-dimensional image representations, so processing power, memory bandwidth/capacity and efficient data movement matter.
Research noteRecord one reason CPU-only execution can be slow for highly parallel ML workloads and one hardware characteristic that can improve throughput. Save detailed GPU comparison for the later CPU/GPU lesson.

Use the dedicated 2027 Case Study Hub to keep one research record across the course.

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Apply

Transfer to a new scenario

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ScenarioA school upgrading computers for graphics, coding and machine learning needs a design or technical decision related to today’s topic. Explain what matters and why.
  • Units: arithmetic logic unit (ALU), control unit (CU)
  • Registers: instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC)
  • Random-access memory (RAM), read only memory (ROM), cache (L1, L2, L3), registers
  • The interaction of the CPU with different types of memory to optimize performance
  • The basic operations a CPU performs to execute a single instruction in machine language
  • The interaction between memory and registers via the three buses: address, data, control
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Exam lens

Paper 1 practice

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Build the response before checking notesUse precise terminology and match the required depth.
  1. Describe: The functions and interactions of the main CPU components in the context of a school upgrading computers for graphics, coding and machine learning.
  2. Explain: The purposes of different types of primary memory in the context of a school upgrading computers for graphics, coding and machine learning.
  3. Describe: The fetch, decode and execute cycle in the context of a school upgrading computers for graphics, coding and machine learning.
Self-checkAnswer the exact command term. For explain, include mechanism/reason; for compare, pair criteria; for discuss/evaluate/justify, build supported reasoning and a conclusion.
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Homework

Finish the learning cycle

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IA — main task

Continue Criterion D development. Keep code readable, record meaningful implementation decisions, and maintain testing/evidence notes as you work.

Syllabus — short

Complete one targeted Paper 2/Paper 1 retrieval task from today’s lesson.

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End of Lesson 29.