CPU architecture, memory and fetch–decode–execute
Trace how CPU components, registers, buses and primary memory cooperate to execute one machine-language instruction.
Follow the instruction through the machine
- describe the functions and interactions of the arithmetic logic unit (ALU), control unit, specified registers and three buses;
- distinguish single-core, multi-core and co-processor roles at a high level;
- explain the purposes of RAM, ROM, cache (L1/L2/L3) and registers, including cache hits/misses;
- describe the fetch, decode and execute cycle using the correct memory/register/bus interactions.
Rapid Recall Deck
Attempt each card first. If a term is new, flip and study it, then answer it again without looking. Mark only secure recall as “Know it”.
CPU components communicate through the buses
CPU
┌──────────────────────────────────┐
│ Control Unit ALU │
│ │
│ PC MAR MDR IR AC │
└──────────────────────────────────┘
│ │ │
address data control buses
│ │ │
┌──────────────────────┐
│ Main memory │
│ RAM / ROM │
└──────────────────────┘Explain the traffic
Use the reference on this page to explain one CPU memory-read exchange. For each of the address, data and control buses, state what it carries and identify where it is used in the exchange.
The address bus carries the memory address selected by the CPU, for example the address held in the MAR. The data bus carries the actual instruction or data value between memory and the CPU, often via the MDR. The control bus carries signals such as memory read/write and timing/control information so the transfer happens correctly.
Register roles matter because the cycle is a sequence
Trace one instruction fetch
The PC currently contains address 240. Memory location 240 contains the next machine-language instruction.
- The address in the PC is copied to the MAR.
- The MAR value is placed on the address bus and the control unit signals a memory read on the control bus.
- The instruction from memory travels on the data bus into the MDR.
- The instruction is copied from MDR to the IR.
- The PC is advanced so it identifies the next instruction.
The control unit coordinates; the ALU computes
Decode → execute
After an instruction reaches the IR, describe what happens during decode and execute. Include the control unit and ALU where relevant.
During decode, the control unit interprets the opcode/operands in the IR and determines the required operation and data movement. During execute, the control unit coordinates the operation; the ALU performs arithmetic/logic when needed, registers may supply/store operands/results, and memory may be read or written through the buses.
Accumulator focus
An ADD instruction produces an intermediate arithmetic result needed by the next instruction. Explain the role of the accumulator.
The accumulator provides fast temporary storage for an intermediate arithmetic/logic result so the CPU can use it in subsequent processing without first writing the value back to slower main memory.
Different memory types solve different access needs
Memory hierarchy
A program repeatedly reuses the same instructions and data. Explain why cache can improve performance and distinguish a cache hit from a cache miss.
Cache keeps recently/frequently used instructions or data close to the CPU. On a cache hit, the item is found in cache and can be accessed quickly. On a cache miss, the CPU must obtain it from a slower memory level such as RAM, increasing access time.
Primary-memory choice
Match each need to registers, cache, RAM or ROM: current CPU operand; frequently reused CPU data; active program working space; persistent startup firmware.
Current operand → register. Frequently reused CPU data → cache. Active program working space → RAM. Persistent startup firmware → ROM.
General-purpose and specialized processing
Processor roles
Describe the difference in role between a single-core processor, a multi-core processor and a co-processor.
A single-core processor has one main processing core executing instruction streams. A multi-core processor contains multiple cores that can work on separate tasks/threads in parallel when software permits. A co-processor is a specialized processor that assists the main CPU with particular categories of work, allowing task division between general-purpose and specialized processing.
Paper 1 rewards precise component interactions
Paper 1-style mini-set
1. Describe the function of the accumulator.
2. Explain how a cache miss can affect CPU performance.
3. Describe the fetch stage using PC, MAR, MDR, IR and the three buses.
- The accumulator temporarily stores intermediate arithmetic/logic results for CPU operations.
- A miss means the required item is not in fast cache; it must be fetched from slower memory, increasing latency and potentially stalling processing.
- A complete description moves PC → MAR, uses address/control buses to request memory, transfers the instruction on the data bus into MDR, copies it to IR and updates PC.
Finish the learning cycle
IA — main task
Continue Criterion D development/testing. Record one implementation decision and one piece of evidence that demonstrates it works.
Paper 1 — short practice
Redraw the CPU/register/memory relationship from memory and narrate one full fetch–decode–execute cycle aloud.