CPU/GPU, pipelining + A1 Paper 1 synthesis
Complete the remaining HL hardware content, connect it to generative-image computation and verify the whole A1 block under Paper 1 conditions.
Finish A1 by linking architecture to workload
- describe GPU architecture/roles in graphics, AI, machine learning and large simulations;
- explain CPU/GPU differences in design, cores, processing, memory access and power efficiency;
- explain CPU/GPU cooperation through task division, data sharing and coordinated execution;
- describe fetch–decode–execute–write-back pipelining and independent multi-core parallel work;
- retrieve and apply the full A1 scope in a cumulative Paper 1 checkpoint.
Rapid Recall Deck
Attempt each card first. If a term is new, flip and study it, then answer it again without looking. Mark only secure recall as “Know it”.
Architecture follows workload
Explain CPU vs GPU
A workstation runs an interactive operating system, prepares batches of image tensors and performs millions of similar mathematical operations on those tensors. Explain which work better fits the CPU, which better fits the GPU, and how the two processors cooperate. Include one point about memory access or power/throughput efficiency.
The CPU has fewer, more general-purpose cores optimized for flexible control, sequential/branch-heavy work and low-latency coordination. The GPU has many simpler processing units aimed at high-throughput parallel operations. GPU memory systems are designed to feed parallel workloads efficiently, while CPU memory hierarchies favour general-purpose locality/latency. For large repeated tensor operations, a GPU can provide much higher throughput and better performance per unit of suitable work, while the CPU remains valuable for OS control, task preparation and irregular logic. The CPU prepares/coordinates work and data transfers; the GPU executes the parallel kernels, then results are shared back for later processing.
Overlap fetch, decode, execute and write-back
Clock step Stage 1 Stage 2 Stage 3 Stage 4 ----------------------------------------------------------------- 1 I1 fetch 2 I2 fetch I1 decode 3 I3 fetch I2 decode I1 execute 4 I4 fetch I3 decode I2 execute I1 write-back
Describe the performance idea
Why can this pipeline complete instructions at a higher overall rate than processing I1 through all four stages before even fetching I2?
The stages of different instructions overlap. While one instruction executes or writes back, later instructions can already be decoding/fetching. After the pipeline fills, multiple instructions are in progress simultaneously, increasing instruction throughput even though each individual instruction still passes through the required stages.
Two different forms of overlap
Multi-core parallelism
A program contains four independent image-processing jobs. Explain how a four-core CPU could improve total completion time compared with one core, assuming the workload and software permit parallel execution.
Different cores can execute separate independent jobs concurrently rather than one core completing every job sequentially. The OS/runtime must divide/schedule the tasks, and real speed-up depends on overhead and how independent the work is.
Pipeline ≠ cores
Distinguish pipelining from multi-core parallelism.
Pipelining overlaps different stages of multiple instructions within a processing pipeline. Multi-core parallelism uses separate processing cores to execute different instruction streams/tasks at the same time. They are different mechanisms and can coexist.
Compute is part of the diffusion challenge
Connect hardware to the diffusion challenge
Visionary Studios uses repeated neural-network denoising. Explain how GPU parallelism, CPU coordination, memory/data movement and scalable deployment resources can affect the performance and feasibility of this workload.
Neural-network denoising involves large numbers of similar matrix/tensor operations that can be distributed across many GPU processing units. The CPU can coordinate the program, prepare data, schedule work and manage I/O. Performance also depends on keeping model parameters/intermediate tensors available and moving data efficiently between memory and processors; insufficient capacity or slow transfer can become a bottleneck. Cloud infrastructure can provide on-demand access to GPU-equipped compute resources, trading local ownership for provider-managed resource availability/cost.
A1.1 + A1.2 retrieval
A1 cumulative checkpoint · Hardware + representation
1. Describe the role of MAR and MDR during a memory read.
2. Explain a cache hit versus cache miss.
3. Convert 7B₁₆ to binary.
4. State the output of XOR for inputs 1 and 0.
5. Explain one reason lossless compression is required for source code.
- MAR holds the memory address being accessed; MDR holds the data/instruction transferred to/from that address.
- Hit: item found in cache and accessed quickly. Miss: item absent, requiring a slower memory-level access.
01111011₂.- 1.
- Source code must be reconstructed exactly; losing characters/bits can change or corrupt the program.
A1.3 + A1.4 retrieval
A1 cumulative checkpoint · OS + control + translation
1. Outline OS accounting.
2. Compare FCFS and round robin.
3. Evaluate interrupts for an unpredictable battery-powered input device.
4. Explain feedback in a thermostat.
5. Explain why compiled code can execute faster than interpreted code.
- Tracks resource usage for monitoring, quotas, analysis or billing.
- FCFS runs by arrival order and can let long jobs delay others; round robin shares repeated time slices, improving responsiveness/fairness but adding switching overhead.
- Interrupts avoid repeated polling when events are unpredictable and can save CPU/power, while still requiring interrupt/security overhead to be controlled.
- The thermostat measures current temperature, compares it with a target, changes heating/cooling, then re-measures the result and adjusts later output.
- Compilation translates/optimizes before execution, so runtime does not repeatedly interpret each source statement and can execute native/target instructions directly.
Connect concepts, then target the remaining gap
Final A1 comparison
A cloud AI service needs rapid development, GPU acceleration and the ability to scale resources. Explain how PaaS/cloud resources, CPU/GPU task division and translation/runtime choice can each affect the system.
A managed platform can reduce infrastructure administration and provide scalable resources; GPU-equipped compute can accelerate parallel neural-network operations while CPUs handle coordination/general work; an interpreted or managed runtime may speed development, while compiled/JIT-optimized hot code can improve performance. The design balances development speed, control, portability, resource availability and execution efficiency.
Gap diagnosis
Which A1 area is currently least secure: hardware/FDE, storage/cloud, data representation, Boolean logic, OS/scheduling, polling/multitasking, control systems or translation?
Finish the learning cycle
IA — main task
Continue Criterion D wrap-up according to your current IA schedule. Be ready to explain the implementation choices and tests in your own words.
Paper 1 — short practice
Redo only the A1 checkpoint areas you missed. Then complete one timed mixed Paper 1 A1 set from your available course practice without notes.
Checkpoint
Update the Case Study Hub with one concise note linking diffusion compute cost to GPU parallelism, memory/data movement and cloud deployment.